1. Field of the Invention
The present invention relates to an IEEE 802.15.4 receiver in use for ZigBee communication and so on, and more particularly, an IEEE 802.15.4 receiver having a digital timing recovery function, which can detect frequency offset of a received signal by using symbol correlation between the received signal and a reference signal, and then recover symbol timing of the received signal according to the degree of the detected offset.
2. Description of the Related Art
In general, IEEE 802.15.4 refers to standards for Low-Rate Wireless Personal Area Network (LR-WPANs). IEEE 802.15.4 is a communication system which divides frequency band into three (3) sub-bands, and sets up spreading policies and data rates different according to the sub-bands. IEEE 802.15.4 which targets small-sized, low power and low cost products is directing attention from local area communication markets, which provide wireless networking of about 10 to 20 m distance to houses or offices, and as a key technology for ubiquitous computing that is currently getting popular.
According to IEEE 802.15.4, data is transmitted/received by using shift type symbol waveform coding, which will be described in brief as follows: A transmitting part maps 4 bit data to one of preset 16 symbols (i.e., 4 bit data needs 16 (24) symbols) and transmits 32 chip signals of the mapped symbol on an RF signal. Then, a receiving part clears off carrier wave from the RF signal, demodulates the RF signal into chip signals through AD conversion, collects the 32 chip signals into a symbol, and recovers original data by correlating the collected symbol with a reference symbol.
FIG. 1 is a block diagram of a conventional IEEE 802.15.4 receiver. Referring to FIG. 1, the conventional receiver includes an analog/digital converter (ADC) 11 for converting an analog signal, which is obtained by clearing off carrier wave from an RF signal, into a digital signal according to a predetermined sampling frequency, a demodulator 12 for demodulating the digital signal, a correlator array 13 for generating correlation value according to 16 symbols through symbol-by-symbol correlation on a chip signal demodulated by the demodulator 12 and a symbol detector 14 for detecting a symbol having the maximum value out of correlation value generated by the correlator array 13.
The afore-described receiver essentially has to execute symbol synchronization in order to detect correct symbols. Examples of such symbol synchronization can include various technologies such as early-late gate technology, digital Phase Lock Loop (PLL) technology and Delay Lock Loop (DLL) technology.
Various conventional synchronization techniques like this have similarity in that they generally achieve synchronization with a received signal by extracting an original clock component from the received signal using a complicated differential circuit, or controlling the sampling frequency of a Voltage Controller Oscillator (VCO) by comparison of the extracted clock component with an internal reference clock.
In particular, FIG. 1 shows an IEEE 802.15.4 receiver block having a symbol synchronization circuit based upon early-late gate technique of conventional synchronization techniques. In FIG. 1, a symbol synchronization circuit 20 includes two integrators 21 and 22 for integrating an output signal from the demodulator 12 in two different integration ranges, a comparator 23 for comparing two integral values from the two integrators 21 and 22, a filter 24 for filtering an output value from the comparator 23 and a Voltage Control Oscillator (VCO) 25 for regulating sampling frequency according to an output value from the filter 24.
The operation of the symbol synchronization circuit 20 will now be described with reference to FIG. 2. An output signal from the demodulator 12 (see FIG. 1) is integrated according to different integration ranges by the two integrators 21 and 22 (see FIG. 1). With a synchronized output signal S12, integration ranges R11 and R21 by the two integrators 21 and 22 become equal as shown in FIG. 2(a), such that the comparator 23 (see FIG. 1) outputs 0. On the other hand, with an unsynchronized output signal S12, an integration range R12 by the integrator 21 decreases by a certain value Δ as shown in FIG. 2(b). Referring to FIG. 2(b), an integration range R22 by the integrator 22 is larger than the integration range R12 by the first integrator 12, such that the comparator 23 outputs a negative value. When the output value from the comparator 23 is applied to the VCO 25 (see FIG. 25) via the filter 24 (see FIG. 1), the VCO 25 corrects oscillation frequency and phase in such a fashion that this phase difference can be corrected, and provides corrected output value to the ADC 11, such that synchronization can be enabled.
Other conventional symbol synchronization circuits such as PLL and DLL symbol synchronization circuits, through comparison of a received signal clock with an internal clock, apply a difference between the clocks to a VCO to adjust oscillation frequency and phase so that the VCO can be synchronized.
In the conventional symbol synchronization circuits using for example early-late gate technique, in order to extract clock components and compare signals, complicated synchronization circuit elements including an integrator, multiplier, a comparator and so on are required in addition to the receiving circuit. This as a result makes entire receiver structure sophisticated and increases the manufacturing cost as well.